Signaling between active devices or integrated circuits (IC's) mounted on computer circuit boards typically relies upon a combination of packages, sockets, connectors, cables, and printed circuit board features to implement a physical interconnection. Referring to FIG. 1, this chip-to-chip communication is often implemented as a number of parallel data interconnects that comprise a bus 22. In some signaling schemes, digital data is represented as the timing of pulses carried on each interconnect with reference to one or more clock signals that are carried on a clock line 24 provided by a common source 26. Forwarded clock signals are typically routed in a manner similar to that of the data signals they accompany. The signals between the input/output (I/O) transceivers 28 and 30 must traverse channel segments both on the IC's 32 and between them 34 that have impairments and are, for practical low cost channel components, less capable of supporting the required data transmission rates than are the transceiver circuits themselves. These impairments include dispersion, crosstalk, loss, reflections due to mismatch, lowpass filtering effects of the channel and other factors that together impose an upper limit on the throughput of the physical link (boards, packages and circuit) at a given maximum Bit Error Rate (BER). Further, the interaction between residual signal components generated by previous symbols can contribute to inter-symbol interference (ISI), which may further limit channel throughput. These impairments to the capacity of the physical channel can be mitigated somewhat by use of higher performance components and circuit board materials, which incur greater cost. Adding additional data lines to a bus will also add cost in terms of both power and board routing space.
Various forms of modulation can be used in place of conventional binary signaling to yield an advantage in data throughput by making greater use of the available channel bandwidth. Practical digital wide-band modulation includes pulse width modulation (PWM), phase modulation (PM), amplitude modulation (AM), and risetime modulation. Many other techniques for improving a channel's binary throughput performance exist including such strategies as transmit and/or receive side equalization and echo cancellation. Return-to-reference or non-return-to-reference differential signaling is commonly used. Many of these signaling schemes may be layered to form phase and amplitude modulation together, for example.
Active elements capable of generating and resolving signal transitions to within narrow time increments can be used in transmitters and receivers in order to implement PM, PWM, and similar modulation schemes in which the locations of signal transitions are varied in time with respect to an embedded or parallel time reference. As illustrated in FIG. 2, digital data may be encoded in terms of a time difference 40 between a signal transition 42 and the precisely known time of occurrence of a transition 44 of a reference clock. For the sake of the discussion, a transition will be assumed to be either a change in level, such as is used in level-based NRZ signaling; or a pulse, such as that used in RZ signaling.
One of the limits on the throughput of the physical link is timing resolution, that is, the precision with which the time difference 40 can be determined. A system that relies on discrimination of the phase of a transition with respect to the phase of a reference transition to achieve time resolution will accumulate temporal measurement variations throughout the duration of the interval 40 separating the signal transition from its timing reference transition. This phenomenon is described as jitter integration. Sources of jitter may include power supply variations or simultaneous switching of other active circuit elements, for example. If the integrated jitter is too high, ambiguity or errors in the classification of the arrival time of a transition may result. It is expected that the jitter will vary over time, being both additive and subtractive, with the greatest potential jitter integration occurring over long timing intervals. One must consider the possibility that all jitter contributions will be additive when setting the worst-case jitter margin.
Simply stated, two time references will accumulate jitter with respect to one another as they pass through dissimilar physical segments, typically active elements, in a circuit. Signals that emanate from a common source are considered to be identical, and initially have zero jitter with respect to one another. It is an accepted practice to assume that signals that pass through similar adjacent circuit elements that share the same power supply will jitter together with high correlation and with little net difference in their relative phase. The jitter statistics of a signal will be preserved as it transits passive elements comprising similar physical channels, and may increase further due to other sources such as electromagnetic interference (EMI), and crosstalk.
In a system using a data bus, jitter integration increases as the time difference 40 separating the transitions of a data line and adjacent reference clock transitions increase. Reducing a data channel's time difference 40 reduces the error in phase measurement caused by jitter accumulation. In some systems, the reference clock signal is generated at a rate that is sufficiently high that the inaccuracy in measured delay is minimized. The clock transitions 44 may also be aligned with data line transitions 42 to further reduce relative timing errors. The clock reference is then forwarded with the data signals in the bus using matched circuit and board structures. Since the physical channel frequently serves to limit the frequency spectrum content of transmitted signals, a limit is often reached in the rate that this clock can be run. Another limiting factor on the clock is electromagnetic EMI emissions, which often increase with frequency and must meet regulatory and system requirements related to EMI pickup of other system components.
In a phase-modulated system, the modulator and demodulator circuits can use the nearest reference clock transition as a timing reference, thereby minimizing the time-distance from the reference and resulting jitter integration. For an ideal (maximum number of possible symbols) phase modulation scheme, data line transitions are permitted over a continuous range of phase positions, with respect to the reference clock. This allows an arbitrarily large symbol set that could provide infinite data throughput. The practical barrier to achieving this throughput is the limited precision that is possible in localizing a transition's discrete location in time, largely due to circuit and ISI jitters. Using a single clock reference with a phase modulation scheme having several phase slots means that the time distance of transitions of the data line to those of the clock will vary, depending on which modulation state was generated. A designer typically assumes a conservative, worst-case jitter margin that ensures that jitter does not lead to mis-classification (bit error) of the phase of an incoming data signal.